Changes Made

1. The main issue was in the backend processing, specifically in the synthesis.py file within the synthesis_module function, so I modified it to fix the problem.
2. Restructured the overall process_wire function to properly store and map multiple wires. The wire_check_source and wire_check_target dictionaries now store intermediate wires by checking the wire ports (i.e., input-out, output-in).
3. After refining the valid_wires, the wires are checked against blocks with global ports. Based on the source and target, wires are connected. If multiple wires are present, another iteration connects all new wires to the relevant port.
4. Removed duplicate wires using a set. This process continues until all wires are mapped correctly.

Related Issues

Fixes: #338

Build zip file

Test_Ckt_Build.zip

Screenshots

Data.json with missing wires:

After resolving data.json (1):

After resolving data.json (2):

Output log:

Circuit image: